sparkfun-dev-08458 / README

This is an example project for the SparkFun DEV-08458 Spartan 3E Breakout and
Development Board. It divides the board's 50MHz clock to produce two slower
signals. It outputs a very slow signal (3Hz) on P2 that is suitable for driving
an LED. It outputs a faster signal (763Hz) on P4 that is best viewed with an
oscilloscope or Bus Pirate.

Warning
=======

Your FPGA is NOT 5V tolerant and the board is configured to use 3.3V for the IO
banks. I am not responsible if you break something.

Did I mention that your FPGA is NOT 5V tolerant?

Dependencies
============

 * SparkFun DEV-08458 and 5V power supply
 * Xilinx ISE
 * A working JTAG cable

What's Included
===============

 * sparkfun-dev-08458.v
   The Verilog file for the design.

 * sparkfun-dev-08458.ucf
   A constraint file that tells the Xilinx tools which IO ports to use. Without
   it, PAR will assign the design's pins to random locations and the design
   will not work.

 * sparkfun-dev-08458.cmd
   An impact batch command script that uploads the design to the FPGA and
   Flash. It assumes that you have a working JTAG cable that impact can
   auto-detect.

 * README
   This file.

 * COPYING
   The license terms (GPLv3).

Instructions
============

 1. Connect an oscilloscope, Bus Pirate, or LED to P2 and/or P4.

    +-------------+
    | Bank 3 Pins |
    +------+------+
    | P2   | P2   |
    | P4   | P4   |
    | GND  | P10  |
    +------+------+

    If you use an oscilloscope, connect GND to P10 and the probe to P2 or P4.

    If you use a Bus Pirate, connect GND to P10 and AUX to P2 or P4.

    If you use an LED, connect the anode to P2 through a current limting
    resistor and connect the cathode to P10.

      P2 ----/\/\/----|>---- P10 (GND)
              330

    The resistor is important: the FPGA is not designed to supply much current.
    Assuming a typical LED with a forward voltage drop of 2V, a 330 ohm
    resistor will keep the current safely below 5mA.

    You can also safely connect an LED to P4 but the signal frequency is too
    fast to see. It will merely dim the LED (PWM dimming). It also needs a
    current limiting resistor.

      P4 ----/\/\/----|>---- P10 (GND)
              330

 2. Connect your JTAG cable. On some revisions of the DEV-08458 the silkscreen
    for the 6-pin JTAG header (header "F") has the TMS and TDO pins swapped. It
    is only a labeling problem; the header is correct with respect to the
    SparkFun and Digilent 6-pin JTAG programmers.

    The pin order for the 6-pin header is:

      1. TMS
      2. TDI
      3. TDO
      4. TCK
      5. GND
      6. VDD (sometimes called VREF or VTARGET)

  3. Set the DEV-08458 header "D" jumpers for "M/SPI" mode (Master SPI). M0 has
     no jumper. M1 and M2 have a jumper.

  4. Connect power to the DEV-08458.

  5. Source the Xilinx settings script. For 32-bit:

       $ . /path/to/Xilinx/13.3/ISE_DS/settings32.sh

     For 64-bit:

       $ . /path/to/Xilinx/13.3/ISE_DS/settings64.sh

  6. Build the design and program the board. The "xflow" command is a sort of
     "make" for the Xilinx toolchain and "impact" is the JTAG programming
     utility.

     The whole process is CPU intensive. It may take more than five minutes to
     run. It will also generate a tremendous amount of output to your screen
     and fill your working directly with dozens of files.

     NOTE: The xflow commands use "sparkfun-dev-08458" without any suffix. It
     is important to always use the base design name without any suffix or
     xflow will be confused.

     6.1. Synth

       This step compiles the Verilog design.

       $ xflow -p xc3s500e-pq208-5 -synth xst_verilog sparkfun-dev-08548

     6.2. Implement

       This step maps the design to the FPGA and its resources.

       $ xflow -p xc3s500e-pq208-5 -implement fast_runtime sparkfun-dev-08548

     6.3. Config

       This step converts the design into a configuration bitstream file that
       will be loaded into the FPGA.

       $ xflow -p xc3s500e-pq208-5 -config bitgen sparkfun-dev-08548

     6.4. Impact

       This step converts the configuration file into a format that can be
       loaded into the board's Flash and then it uploads that data into the
       board via JTAG.

       $ impact -batch sparkfun-dev-08458.cmd

     At the end of the build process the board's "DONE" light will turn off
     while the FPGA resets and loads the design from the Flash. The process is
     complete once the "DONE" light turns back on and impact exits without an
     error.

  7. Observe the signals with your oscilloscope, Bus Pirate, or LED.

     For verification with the Bus Pirate, use the Frequency Counter ("F"):

       HiZ>F
       Frequency on AUX pin: 512Hz

     Don't be surprised if the observed frequency isn't exactly what you
     expect. It is influenced by many factors including temperature. In the
     example above my Bus Pirate is being dodgy. An actual calibrated frequency
     counter observed 2.98Hz and 762.9Hz.

Math
====

  The signals are generated by simply by routing bits from the counter out to
  the IO ports. The oscillator frequency is 50MHz. The counter is 24 bits wide.
  P2 uses the counter's 24th bit and therefore divides the clock frequency by
  2^24 (16,777,216). P4 uses the counter's 16th bit and therefore divides the
  clock frequency by 2^16 (65,536).

  Frequency of P2:   3Hz ~ 50MHz / 2^24
  Frequency of P4: 763Hz ~ 50MHz / 2^16